Jumper cap circuit and method for designing the same

ABSTRACT

A jumper cap circuit and a method for designing the same are provided. The jumper cap circuit includes: a three-pin header, a chip, a pull-up resistor or a pull-down resistor, and a resistor R 1 . The header is connected to the chip via the pull-up resistor or the pull-down resistor, and a voltage dividing circuit is constituted by the resistor R 1  and the pull-up resistor or the pull-down resistor, and the resistor R 1  is connected to a pin of the pin header. The method includes: acquiring a default input state of a chip, and setting, based on the default input state of the chip, a default value of the chip by arranging a first resistor in a path where a first pin of the three-pin header is located and arranging a second resistor in a path where a second pin of the three-pin header is located.

The present application claims the priority to Chinese PatentApplication No. 201810729944.0, titled “JUMPER CAP CIRCUIT AND METHODFOR DESIGNING THE SAME”, filed on Jul. 5, 2018 with the Chinese PatentOffice, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the technical field of designingserver systems, and in particular to a jumper cap circuit and a methodfor designing the same.

BACKGROUND

A motherboard of a server is generally provided with a variety ofheaders and jumper caps. A level of a signal supplied to the header maybe changed by changing a position of a jumper cap, thus parameters ofthe header are set to suit for a chip. In a case that the server isoriginally manufactured, default parameters are set for the server, toensure a normal operation of the server for a first usage. These defaultparameters are set by connecting the jumper cap to different pins of theheader.

A connection manner in a conventional jumper cap circuit is as shown inFIG. 1. As shown in FIG. 1, for setting parameters, a pin1 of athree-pin header is connected to a power supply Vcc, a pin2 of thethree-pin header is connected to a chip, and a pin3 of the three-pinheader is connected to the ground GND. The three-pin header is generallyused to set two default parameters. One default parameter represents ahigh level, which is realized by connecting the pin1 and the pin2 with ajumper cap, thus a signal inputted to the chip is at a high level, whichis defined as a logic 1. The other one default parameter represents alow level, which is realized by connecting the pin2 and the pin3 with ajumper cap, thus a signal inputted to the chip is at a low level, whichis defined as logic 0.

However, the jumper cap may be fell off due to vibration during thetransportation of a server, and there is no protective measure providedfor the connection manner in the conventional circuit for settingdefault parameters. As a result, a signal line connected to the pin 2 isfloated if the jumper cap is fell off, thereby resulting in an abnormaloperation of the chip, thus affecting the performance of the server.

SUMMARY

A jumper cap circuit and a method for designing a jumper cap circuit areprovided according to the present disclosure, to solve a problem in theconventional art that a chip fails to operate normally once a jumper capis fell off due to the connection manner in a circuit.

In order to solve the above problem, the following technical solutionsare provided according to embodiments of the present disclosure.

A jumper cap circuit is provided, which includes a three-pin header anda chip, a pull-up resistor or a pull-down resistor, and a resistor R1.The three-pin header is connected to the chip via the pull-up resistoror the pull-down resistor. The resistor R1 and the pull-up resistorconstitute a voltage dividing circuit or the resistor R1 and thepull-down resistor constitute a voltage dividing circuit. The resistorR1 is connected to a pin of the three-pin header. A resistance of theresistor R1 is equal to or greater than ten times of that of the pull-upresistor. The resistance of the resistor R1 is equal to or greater thanten times of that of the pull-down resistor.

Optionally, if a default input state of the jumper cap circuit is a highlevel state, the jumper cap circuit comprises a pull-up resistor R2, anda first pin of the three-pin header is grounded via the resistor R1, asecond pin of the three-pin header is connected to the chip after alevel of the second pin is pulled up by the pull-up resistor R2, and athird pin of the three-pin header is grounded via a resistor R3.

Optionally, if a default input state of the jumper cap circuit is a lowlevel state, the jumper cap circuit comprises a pull-down resistor R2which is grounded, and a level of a first pin of the three-pin header ispulled up by the resistor R1, a second pin of the three-pin header isconnected to the chip after a level of the second pin is pulled down bythe pull-down resistor R2, and a level of a third pin of the three-pinheader is pulled up by a resistor R3.

Optionally, the resistance of the resistor R1 is equal to or greaterthan ten times of that of the pull-up resistor R2. The resistance of thepull up resistor R2 is equal to or greater than ten times of that of theresistor R3.

Optionally, the chip is provided with a Strap pin.

A method for designing a jumper cap circuit is further provided, whichis applicable to a jumper cap circuit including a three-pin header and achip. The method includes:

acquiring a default input state of the chip, where the default inputstate comprises a high level state and a low level state; and

setting, based on the default input state of the chip, a default valueof the chip by arranging a first resistor in a path where a first pin ofthe three-pin header is located and arranging a second resistor in apath where a second pin of the three-pin header is located.

The default value of the chip includes logic 0 or logic 1. The secondresistor is a pull-up resistor or a pull-down resistor. The second pinis a pin of the three-pin header which is connected to the chip. Thefirst resistor and the second resistor constitute a voltage dividingcircuit. A resistance of the first resistor is equal to or greater thanten times of that of the second resistor.

Optionally, the setting, based on the default input state of the chip, adefault value of the chip by arranging a first resistor in a path wherea first pin of the three-pin header is located and arranging a secondresistor in a path where a second pin of the three-pin header is locatedincludes:

if the default input state of the chip is a high level state and thesecond resistor is a pull-up resistor, connecting the first pin of thethree-pin header to a ground via the first resistor, and connecting thesecond pin of the three-pin header to the chip after a level of thesecond pin is pulled up by the second resistor.

Optionally, the setting, based on the default input state of the chip, adefault value of the chip by arranging a first resistor in a path wherea first pin of the three-pin header is located and arranging a secondresistor in a path where a second pin of the three-pin header is locatedfurther includes:

connecting a third pin of the three-pin header to the ground via a thirdresistor.

The resistance of the second resistor is equal to or greater than tentimes of that of the third resistor.

Optionally, the setting, based on the default input state of the chip, adefault value of the chip by arranging a first resistor in a path wherea first pin of the three-pin header is located and arranging a secondresistor in a path where a second pin of the three-pin header is locatedincludes:

if the default input state of the chip is a low level state and thesecond resistor is a pull-down resistor which is grounded, pulling up alevel of the first pin of the three-pin header by the first resistor,and connecting the second pin of the three-pin header to the chip aftera level of the second pin is pulled down by the second resistor.

Optionally, the setting, based on the default input state of the chip, adefault value of the chip by arranging a first resistor in a path wherea first pin of the three-pin header is located and arranging a secondresistor in a path where a second pin of the three-pin header is locatedfurther includes:

pulling up a level of a third pin of the three-pin header by a thirdresistor.

The resistance of the second resistor is equal to or greater than tentimes of that of the third resistor.

The following beneficial effects can be realized with the technicalsolutions according to the embodiments of the present disclosure.

A jumper cap circuit is provided according to the present disclosure.The jumper cap includes a three-pin header, a chip, a pull-up resistoror a pull-down resistor, and a resistor R1. The three-pin header isconnected to the chip via the pull-up resistor or the pull-downresistor. The resistor R1 and the pull-up resistor constitute a voltagedividing circuit or the resistor R1 and the pull-down resistorconstitute a voltage dividing circuit. The resistance of the resistor R1is equal to or greater than ten times of that of the pull-up resistor.The resistance of the resistor R1 is equal to or greater than that ofthe pull-down resistor. In a case that the default input state of thejumper cap circuit is a high level state, the jumper cap circuitincludes a pull-up resistor R2, and a first pin of the three-pin headeris connected to the ground via the resistor R1, a second pin of thethree-pin header is connected to the chip after a level of the secondpin is pulled up by the pull-up resistor R2, and a third pin of thethree-pin header is connected to the ground via a resistor R3. In a casethat the default input state of the jumper cap circuit is a low levelstate, the jumper cap circuit includes a pull-down resistor R2 which isgrounded, and a level of the first pin of the three-pin header is pulledup by the resistor R1, the second pin of the three-pin header isconnected to the chip after the level of the second pin is pulled downby the pull-down resistor R2, and a level of the third pin of thethree-pin header is pulled up by the resistor R3. According to thepresent disclosure, in a case that the default input state of the chipis a high level state, the second pin of the three-pin header isconnected to the chip after the level of the second pin is pulled up bythe pull-up resistor, such that an input of the chip remains at a highlevel. A voltage dividing circuit is constituted by the resistor R1 andthe pull-down resistor, such that even if a jumper cap is fell offduring transportation of a server, a voltage supplied to the chipremains at Vcc, that is, the input of the chip is still logic 1. In acase that the default input state of the chip is a low level state, thesecond pin of the three-pin header is connected to the chip after thelevel of the second pin is pulled down by a pull-down resistor which isgrounded, such that an input of the chip remains at a low level. Avoltage dividing circuit is constituted by the resistor R1 and thepull-down resistor, such that even if a jumper cap is fell off duringtransportation of a server, the voltage supplied to the chip is stillzero, that is, the input of the chip is still logic 0. Therefore, withthe connection manner of the three-pin header and the chip in the jumpercap circuit of the present disclosure, the chip can remain at an initialdefault input state even if a jumper cap is fell off, thereby ensuring acorrect logic of the chip, thus ensuring a normal operation of the chip.

In addition, in the present disclosure, the resistance of the firstresistor R1 is equal to or greater than ten times of that of the secondresistor R2, and the resistance of the second resistor is equal to orgreater than ten times of that of the third resistor R3. A balance ofthe circuit can be achieved by setting the resistances of the threeresistors to meet certain conditions. The chip can remain at an initialdefault input state if a jumper cap is not fell off or duringtransportation of a server, which facilitates a further improvement ofreliability of the server.

A method for designing a jumper cap circuit is further providedaccording to the present disclosure. In the method, a default inputstate of a chip is acquired, then a default value of the chip is setbased on the default input state of the chip by arranging a firstresistor in a path where a first pin of the three-pin header is locatedand arranging a second resistor in a path where a second pin of thethree-pin header is located. In a case that the default input state ofthe chip is a high level state, the second resistor serves as a pull-upresistor, the first pin of the three-pin header is connected to theground via the first resistor, and the second pin of the three-pinheader is connected to the chip after a level of the second pin ispulled up by the second resistor. In a case that the default input stateof the chip is a low level state, the second resistor is grounded andserves as a pull-down resistor, a level of the first pin of thethree-pin header is pulled up by the first resistor, and the second pinof the three-pin header is connected to the chip after the level of thesecond chip is pulled down by the second resistor, and the resistance ofthe first resistor is equal to or greater than ten times of that of thesecond resistor. In the present disclosure, a second resistor serving asa pull-up resistor or a pull-down resistor is arranged in the path wherethe second pin of a three-pin header is located based on differentdefault input states, such that the chip can remain at a default inputstate. A voltage dividing circuit is constituted by a first resistor anda second resistor, such that an abnormal operation of the chip due tothe falling off of a jumper cap can be effectively avoided, therebyimproving the reliability of the server. In addition, in a case that thedefault input state of the chip is a high level state, a third pin ofthe three-pin header is connected to the ground via a third resistor,and the resistance of the second resistor is equal to or greater thanten times of that of the third resistor. In a case that the defaultinput state of the chip is a low level state, a level of a third pin ofthe three-pin header is pulled up by the third resistor, and theresistance of the second resistor is equal to or greater than ten timesof that of the third resistor. With the method, a balance of the circuitcan be achieved, and the chip can remain at an initial default inputstate if a jumper cap is not fell off or during the transportation of aserver, which facilities a further improvement of the reliability of theserver.

It is to be understood that the above general description and thefollowing detailed description are merely exemplary and explanatory, anddo not intend to limit the scope of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly describe the technical solution in theembodiments of the present disclosure or the technical solution in theconventional art, drawings to be used in the description of theembodiments of the present disclosure or the conventional art arebriefly described hereinafter. It is apparent that the drawingsdescribed below show merely the embodiments of the present disclosure,and those skilled in the art may obtain other drawings according to theprovided drawings without any creative effort.

FIG. 1 is schematic diagram of a jumper cap circuit in the conventionalart;

FIG. 2 is schematic diagram of a jumper cap circuit according to anembodiment of the present disclosure;

FIG. 3 is schematic diagram of a jumper cap circuit according to anotherembodiment of the present disclosure; and

FIG. 4 is a schematic flow chart of a method for designing a jumper capcircuit according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make those skilled in the art better understand thetechnical solutions of the present disclosure, the technical solutionsin the embodiments of the present disclosure are described clearly andcompletely hereinafter in conjunction with the drawings in theembodiments of the present disclosure. Apparently, the describedembodiments are only some rather than all of the embodiments of thepresent disclosure. All other embodiments obtained by those skilled inthe art based on the embodiments of the present disclosure without anycreative work should fall within the protection scope of the presentdisclosure.

In order to better understand the technical solutions of the presentdisclosure, the embodiments of the present disclosure are described indetail below with reference to the drawings.

Embodiment One

Reference is made to FIG. 2, which is schematic diagram of a jumper capcircuit according to an embodiment of the present disclosure. As shownin FIG. 2, in the present embodiment, the jumper cap circuit includes athree-pin header, a chip, and a pull-up resistor R2. The three-pinheader is connected to the chip via the pull-up resistor R2. In FIG. 2,a pin1 is a first pin, a pin2 is a second pin, a pin3 is a third pin. Aresistor R1 is connected to the first pin. The pull-up resistor R2 isconnected to the second pin, and a resistor R3 is connected to the thirdpin.

In the present embodiment, in the jumper cap circuit, the default inputstate of the chip is a high level state. The first pin is grounded viathe resistor R1, and the second pin is connected to the chip after alevel of the second pin is pulled up by the pull-up resistor R2. Theresistance of the resistor R1 is equal to or greater than ten times ofthat of the pull-up resistor R2.

According to the above arrangement, the resistor R2 serves as a pull-upresistor, the second pin of the three-pin header is connected to thechip after the level of the second pin is pulled up by the resistor R2.The resistor R1 and the pull-up resistor R2 constitute a voltagedividing circuit, such that the input state of the chip remains at ahigh level state. Specifically, in a case that the jumper cap is notfell off, the level of the second pin is pulled up to Vcc by the pull-upresistor R2, and the resistor R1 and the resistor R2 constitute avoltage dividing circuit, such that a voltage supplied to the chip isexpressed by Vcc*R1/(R1+R2). Since the resistance of the first resistorR1 is equal to or greater than ten times of that of the second pull-upresistor R2, the following equation can be derived: Vcc*R1/(R1+R2)−≈Vcc.Therefore, the voltage inputted to the chip is approximately equal toVcc, that is, the input of the chip is logic 1. In a case that thejumper cap is fell off, the second pin of the three-pin header isfloated, and the chip is still connected to the power supply Vcc via theresistor R2, such that the voltage inputted to the chip is still equalto Vcc, that is, the input of the chip is still logic 1.

Therefore, with the jumper cap circuit in the present embodiment, thechip can remain at an initial default input state even if a jumper capis fell off, thereby ensuring a correct logic of the chip, thus ensuringthe normal operation of the chip.

Furthermore, in the jumper cap circuit of the present disclosure, thethird pin of the three-pin header is grounded via the resistor R3, andthe resistance of the pull-up resistor R2 is equal to or greater thanten times of that of the third resistor R3.

Specifically, as can be seen from FIG. 2, in the default input state ofthe jumper cap circuit, the pin1 and the pin2 are connected with ajumper cap, and a voltage supplied to the chip is equal to a voltageacross the resistor R1, thus the voltage supplied to the chip isexpressed by Vcc*R1/(R1+R2). Since the resistance of the first resistorR1 is equal to or greater than ten times of that of the second pull-upresistor R2, the following equation may be derived: Vcc*R1/(R1+R2)≈Vcc,that is, the input of the chip is logic 1. In a case that the pin2 andthe pin3 are connected with a jumper cap, the voltage supplied to thechip is equal to the voltage across the resistor R3, thus the voltagesupplied to the chip is expressed by Vcc*R3/(R2+R3). Since theresistance of the first pull-up resistor R2 is equal to or greater thanten times of that of the second pull-up resistor R3, the followingequation can be derived: Vcc*R3/(R2+R3)≈0, that is, the input of thechip is logic 0. Therefore, in a case that the jumper cap is not felloff, the default input state of the chip is a high level state, that is,the input of the chip is logic 1, and in a case that the jumper cap isfell off, as can be seen from FIG. 2, the second pin of the three-pinheader is floated, the voltage supplied to the chip is Vcc, thus theinput of the chip is still logic 1. Therefore, in the embodiment, theresistances of the three resistors in the jumper cap circuit are set tomeet certain conditions, it can be ensured that the default input stateof the chip is a high level state no matter the jumper cap is fell offor not fell off, thereby ensuring the normal operation of the chip.

In the embodiment, the third pin of the three-pin header is grounded viaa resistor R3, such that the resistor R3 and the pull-up resistor R2constitute a voltage dividing circuit, thus facilitating the balance ofthe circuit. Moreover, the resistor R3 is arranged such that thesubsequent debugging operation on the jumper cap circuit is facilitated.For example, the resistor R3 may be reset to have other resistances tofacilitate the debugging operation on the jumper cap circuit, therebyimproving the flexibility of the jumper cap circuit.

In addition, in the embodiment, the third pin of the three-pin headermay be directly grounded via a wire.

Furthermore, in the present disclosure, the chip is provided with aStrap pin, which is a pin to which a level of an input is determined byan external jumper wire. The Strap pin has a multiplexing function, andmay serve as a multiplexing pin. For example, the Strap pin operates fora certain function during a power-on and reset stage, and operates foranother function during the normal operation. In the present disclosure,the header is a three-pin header, that is, the header has three pins.

Embodiment Two

Based on the embodiment shown in FIG. 2, reference is made to FIG. 3,which is schematic diagram of a jumper cap circuit according to anotherembodiment of the present disclosure. As shown in FIG. 3, in theembodiment, the jumper cap circuit includes a three-pin header, a chip,a pull-down resistor R2, and a resistor R1 for dividing voltage with thepull-down resistor R2. The three-pin header is connected to the chip viathe pull-down resistor R2, and a level of a first pin of the three-pinheader is pulled up to Vcc by the resistor R1. In FIG. 3, a pin1 is afirst pin, a pin2 is a second pin, a pin3 is a third pin. The resistorR1 is connected to the first pin, the pull-down resistor R2 is connectedto the second pin, and a resistor R3 is connected to the third pin.

In the embodiment, the default input state of the chip in the jumper capcircuit is a low level state. The level of the first pin is pulled up bythe resistor R1, and the second pin of the three-pin header is connectedto the chip after a level of the second pin is pulled down by thepull-down resistor R2 which is grounded. The resistance of the firstresistor R1 is equal to or greater than ten times of that of the secondpull-up resistor R2.

According to the above arrangement, the resistor R2 serves as apull-down resistor, the second pin of the three-pin header is connectedto the chip after the level of the second pin is pulled down by theresistor R2, and the resistor R1 and the pull-up resistor R2 constitutea voltage dividing circuit, such that the input state of the chipremains at a low level state. The principle of remaining the input ofthe chip at logic 0 by using the resistor R1 and the resistor R2 in thejumper cap circuit no matter the jumper cap is fell off or not fell offis similar to the principle in the embodiment one of remaining the inputof the chip at logic 1 in the jumper cap circuit, which is not describedin detail herein.

Furthermore, in the embodiment, in the jumper cap circuit, the level ofthe third pin of the three-pin header is pulled up by the resistor R3,and the resistance of the pull-down resistor R2 is equal to or greaterthan ten times of that of the resistor R3.

As can be seen from FIG. 3, in the default input state of the jumper capcircuit, the pin1 and the pin2 are connected with a jumper cap, and avoltage supplied to the chip is equal to a voltage across the pull-downresistor R2, thus the voltage supplied to the chip is expressed byVcc*R2/(R1+R2). Since the resistance of the first resistor R1 is equalto or greater than ten times of that of the second pull-down resistorR2, the following equation may be derived: Vcc*R2/(R1+R2)≈0, that is,the input of the chip is logic 0. In a case that the pin2 and the pin3are connected with a jumper cap, the voltage supplied to the chip isequal to the voltage across the pull-down resistor R2, thus the voltagesupplied to the chip is expressed by Vcc*R2/(R2+R3). Since theresistance of the pull-down resistor R2 is equal to or greater than tentimes of that of the third resistor R3, the following equation may bederived: Vcc*R2/(R2+R3)≈Vcc, that is, the input of the chip is logic 1.If the jumper cap is fell off, as can be seen from FIG. 3, the secondpin is floated, the voltage supplied to the chip is zero, that is, theinput of the chip is still logic 0. Therefore, in the embodiment, theresistances of the three resistors in the jumper cap circuit are set tomeet certain conditions, such that the default input state of the chipis a low level state no matter the jumper cap is fell off or not felloff, thereby ensuring the normal operation of the chip.

In addition, in the embodiment, the level of the third pin of thethree-pin header may be directly pulled up via a wire.

For the part that is not described in detail in the embodiment,reference may be made to the embodiment one as shown in FIG. 2. The twoembodiments may be referred to each other, and details are not repeatedherein.

Embodiment Three

Based on the embodiments as shown in FIG. 2 and FIG. 3, reference ismade to FIG. 4, which is a schematic flow chart of a method fordesigning a jumper cap circuit according to an embodiment of the presentdisclosure. As shown in FIG. 4, in the present disclosure, the methodfor designing a jumper cap circuit mainly includes the following stepsof S1 and S2.

In step S1, a default input state of a chip is acquired, where thedefault input state of the chip includes a high level state and a lowlevel state.

The method of the present disclosure is mainly applicable to a jumpercap circuit including a chip and a three-pin header.

In step S2, a default value of the chip is set based on the defaultinput state of the chip by arranging a first resistor in a path where afirst pin of the three-pin header is located and arranging a secondresistor in a path where a second pin of the three-pin header islocated. The default value of the chip includes logic 0 or logic 1. Thesecond resistor serves as a pull-up resistor or a pull-down resistor,and the second pin of the three-pin header is connected to the chip, andthe first resistor and the second resistor constitute a voltage dividingcircuit. The resistance of the first resistor is equal to or greaterthan ten times of that of the second resistor.

In the present disclosure, a second resistor serving as a pull-upresistor or a pull-down resistor is arranged in the path where thesecond pin of the three-pin header is located based on different defaultinput states, and the voltage dividing circuit is constituted by thefirst resistor and the second resistor, such that the level of the inputto the chip remains at the default input state, thereby effectivelyavoiding an abnormal operation of the chip due to the falling off of ajumper cap, thus improving the reliability of the server.

Specifically, the step S2 is performed in the following two cases.

In one case, the default input state of the chip is a high level state,the second resistor serves as a pull-up resistor, the first pin of thethree-pin header is grounded via the first resistor, and the second pinof the three-pin header is connected to the chip after the level of thesecond pin is pulled up by the second resistor.

Further, a third pin of the three-pin header is grounded via a thirdresistor, where the resistance of the second resistor is equal to orgreater than ten times of that of the third resistor.

In another case, the default input state of the chip is a low levelstate, the second resistor is grounded and serves as a pull-downresistor, the level of the first pin of the three-pin header is pulledup by the first resistor, and the second pin of the three-pin header isconnected to the chip after the level of the second pin is pulled downby the second resistor.

Further, the level of the third pin is pulled up by the third resistor,and the resistance of the second resistor is equal to or greater thanten times of that of the third resistor.

In the embodiment, the operation principle and the operation method ofthe jumper cap circuit is described in detail in the embodiments asshown in FIG. 2 and FIG. 3. The three embodiments may be referred toeach other, and details are not repeated herein.

The embodiments described above only specific embodiments of the presentdisclosure, which are used to understand or implement the presentdisclosure by those skilled in the art. It is apparent that variousmodifications to these embodiments may be made by those skilled in theart, and the general principles defined in the present disclosure may beimplemented in other embodiments without departing from the principle orscope of the present disclosure. Therefore, the present disclosure isnot limited to the embodiments described herein, but complies with thebroadest scope consistent with the principles and novel featuresdisclosed herein.

1. A jumper cap circuit, comprising: a three-pin header; a chip; apull-up resistor or a pull-down resistor, wherein the three-pin headeris connected to the chip via the pull-up resistor or the pull-downresistor; and a resistor R1, wherein the resistor R1 and the pull-upresistor constitute a voltage dividing circuit or the resistor R1 andthe pull-down resistor constitute a voltage dividing circuit, and theresistor R1 is connected to a pin of the three-pin header, and wherein aresistance of the resistor R1 is equal to or greater than ten times ofthat of the pull-up resistor; and the resistance of the resistor R1 isequal to or greater than ten times of that of the pull-down resistor. 2.The jumper cap circuit according to claim 1, wherein if a default inputstate of the jumper cap circuit is a high level state, the jumper capcircuit comprises a pull-up resistor R2, and a first pin of thethree-pin header is grounded via the resistor R1, a second pin of thethree-pin header is connected to the chip after a level of the secondpin is pulled up by the pull-up resistor R2, and a third pin of thethree-pin header is grounded via a resistor R3.
 3. The jumper capcircuit according to claim 1, wherein if a default input state of thejumper cap circuit is a low level state, the jumper cap circuitcomprises a pull-down resistor R2 which is grounded, and a level of afirst pin of the three-pin header is pulled up by the resistor R1, asecond pin of the three-pin header is connected to the chip after alevel of the second pin is pulled down by the pull-down resistor R2, anda level of a third pin of the three-pin header is pulled up by aresistor R3.
 4. The jumper cap circuit according to claim 2, wherein theresistance of the resistor R1 is equal to or greater than ten times ofthat of the pull-up resistor R2, and the resistance of the pull-upresistor R2 is equal to or greater than ten times of that of theresistor R3.
 5. The jumper cap circuit according to claim 1, wherein thechip is provided with a Strap pin.
 6. A method for designing a jumpercap circuit, wherein the method is applicable to a jumper cap circuitcomprising a three-pin header and a chip, and the method comprises:acquiring a default input state of the chip, wherein the default inputstate comprises a high level state and a low level state; and setting,based on the default input state of the chip, a default value of thechip by arranging a first resistor in a path where a first pin of thethree-pin header is located and arranging a second resistor in a pathwhere a second pin of the three-pin header is located, and wherein thedefault value of the chip comprises logic 0 or logic 1, the secondresistor is a pull-up resistor or a pull-down resistor, and the secondpin is a pin of the three-pin header which is connected to the chip, andthe first resistor and the second resistor constitute a voltage dividingcircuit, and a resistance of the first resistor is equal to or greaterthan ten times of that of the second resistor.
 7. The method fordesigning a jumper cap circuit according to claim 6, wherein thesetting, based on the default input state of the chip, a default valueof the chip by arranging a first resistor in a path where a first pin ofthe three-pin header is located and arranging a second resistor in apath where a second pin of the three-pin header is located comprises: ifthe default input state of the chip is a high level state and the secondresistor is a pull-up resistor, connecting the first pin of thethree-pin header to a ground via the first resistor, and connecting thesecond pin of the three-pin header to the chip after a level of thesecond pin is pulled up by the second resistor.
 8. The method fordesigning a jumper cap circuit according to claim 7, wherein thesetting, based on the default input state of the chip, a default valueof the chip by arranging a first resistor in a path where a first pin ofthe three-pin header is located and arranging a second resistor in apath where a second pin of the three-pin header is located furthercomprises: connecting a third pin of the three-pin header to the groundvia a third resistor, and wherein the resistance of the second resistoris equal to or greater than ten times of that of the third resistor. 9.The method for designing a jumper cap circuit according to claim 6,wherein the setting, based on the default input state of the chip, adefault value of the chip by arranging a first resistor in a path wherea first pin of the three-pin header is located and arranging a secondresistor in a path where a second pin of the three-pin header is locatedcomprises: if the default input state of the chip is a low level stateand the second resistor is a pull-down resistor which is grounded,pulling up a level of the first pin of the three-pin header by the firstresistor, and connecting the second pin of the three-pin header to thechip after a level of the second pin is pulled down by the secondresistor.
 10. The method for designing a jumper cap circuit according toclaim 9, wherein the setting, based on the default input state of thechip, a default value of the chip by arranging a first resistor in apath where a first pin of the three-pin header is located and arranginga second resistor in a path where a second pin of the three-pin headeris located further comprises: pulling up a level of a third pin of thethree-pin header by a third resistor, and wherein the resistance of thesecond resistor is equal to or greater than ten times of that of thethird resistor.
 11. The jumper cap circuit according to claim 3, whereinthe resistance of the resistor R1 is equal to or greater than ten timesof that of the pull-down resistor R2, and the resistances of thepull-down resistor R2 is equal to or greater than ten times of that ofthe resistor R3.
 12. The jumper cap circuit according to claim 2,wherein the chip is provided with a Strap pin.
 13. The jumper capcircuit according to claim 3, wherein the chip is provided with a Strappin.